Encoding:

Format:

SHRA[_R].PH 

SHRA.PH   rt, rs, sa

SHRA_R.PH rt, rs, sa

Purpose:

Shift Right Arithmetic Vector Pair Halfwords

Element-wise arithmetic right-shift of two independent halfwords in a vector data type by a fixed number of bits, with optional rounding.

Description:

rt = rnd16(rs31..16 >> sa) || rnd16(rs15..0 >> sa)

The two halfword values in register rt are each independently shifted right by sa bits, with each value’s original sign bit duplicated into the sa most-significant bits emptied by the shift.

In the non-rounding variant of this instruction, the two independent results are then written to the corresponding halfword elements of destination register rd.

In the rounding variant of the instruction, a 1 is added at the most-significant discarded bit position before the results are written to destination register rd.

Restrictions:

No data-dependent exceptions are possible.

The operands must be values in the specified format. If they are not, the results are UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation:

SHRA.PH
   ValidateAccessToDSPResources()
   tempB15..0 = shift16RightArithmetic( GPR[rs]31..16, sa )
   tempA15..0 = shift16RightArithmetic( GPR[rs]15..0, sa )
   GPR[rt]31..0 = tempB15..0 || tempA15..0
SHRA_R.PH
   ValidateAccessToDSPResources()
   tempB15..0 = rnd16ShiftRightArithmetic( GPR[rs]31..16, sa )
   tempA15..0 = rnd16ShiftRightArithmetic( GPR[rs]15..0, sa )
   GPR[rt]31..0 = tempB15..0 || tempA15..0
function shift16RightArithmetic( a15..0, s3..0 )
   if ( s3..0 = 0 ) then
      temp15..0 = a15..0
   else
      sign = a15
      temp15..0 = ( signs || a15..s )
   endif
   return temp15..0
function rnd16ShiftRightArithmetic( a15..0, s3..0 )
   if ( s3..0 = 0 ) then
      temp16..0 = ( a15..0 || 0 )
   else
      sign = a15
      temp16..0 = ( signs || a15..s-1 )
   endif
   temp16..0 = temp + 1
   return temp16..1 
endfunction rnd16ShiftRightArithmetic

Exceptions:

Reserved Instruction, DSP Disabled